1. Field of the Invention
The present invention relates to field-programmable-gate-array (FPGA) integrated circuit technology. More particularly, the present invention relates to on-chip circuits for testing an FPGA for the presence of delay defects.
2. Prior Art
Traditionally, integrated circuits are only tested for functional defects (those that become apparent no matter how slowly the chip is operated). However as semiconductor technology scales, it becomes necessary to check for delay defects as well. A typical example of a delay defect is a contact having an unduly high resistance.
Methods for testing for delay defects in nonprogrammable integrated circuits, such as standard cell ASICs, are known in the prior art. Some of these are applicable also to programmable integrated circuits, including FPGAs. Other testing methods are specific to programmable integrated circuits.
There are three general categories of known test methods: at-speed functional test with the intended design; scan chain testing; and methods specific to programmable logic devices. Each is considered in turn.
In at-speed functional testing, the circuit is tested by running it as in normal operation, but using the highest specified clock frequency. This can be very effective for non-programmable integrated circuits, or for programmable integrated circuits that are already programmed with the intended design and will not be reprogrammed. However for programmable integrated circuits, the need to use the highest specified clock frequency is problematic, since this frequency is very design-dependent and end-user designs are not known at the time of testing.
Scan chains are a widely used technique for performing functional testing of non-programmable integrated circuits (e.g. standard cell ASICs). The various flip-flops in an integrated circuit are connected together to form a shift register scan chain independent of the normal functional logic. By putting the flip-flops in a special scan mode, test data can be shifted into and/or out of the flip-flops.
Scan chains can also be used to test for delay defects. There are two methods for using scan chains to perform delay-defect testing, launch from shift and launch from capture. One example is found in R. Madge, B. R. Benware and W. R Daasch, “Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs, IEEE Design & Test of Computers,” September-October 2003, pp. 46-53.
Common to both methods is that two clock pulses are applied at high speed and path delays exceeding the intervening time are detected. First, a test pattern is loaded using the scan chain. Signals are then launched through the delay paths either by a last pulse of the clock in scan mode (“launch from shift”), or by pulsing the clock in normal mode (“launch from capture”). After a suitable delay, the outputs of the delay paths are captured in the flip-flops by another pulse of the clock, in normal mode. In some cases it may be desirable to pulse the clock multiple times in normal mode before reading out the data.
An FPGA programmed with a particular design can also be tested for delay defects using launch and capture pulses if some means (analogous to a scan chain) is provided to control and observe the flip-flops. In an FPGA, alternatives for controlling and observing the flip-flops include a hard (built-in) scan chain, a soft (programmed as part of the design) scan chain, and a read/write probe circuit using row/column addressing. In the following discussion, the term “scan chain” will be considered to include any of these or other similar means for controlling and observing the flip-flops.
When using launch and capture pulses for delay testing, it is crucial to precisely control the intervening interval, since this governs the time allowed for the signals to propagate through the paths under test. Various circuits and methods for doing so are known in the prior art.
Several examples of such circuits and methods are disclosed in AppNote 5202 of Jul. 15, 2005 from Mentor Graphics, describing an on-chip generator for creating two pulses, one for launch and one for capture, on the same output. The spacing between the pulses is determined by the frequency of an incoming clock, with no ability to adjust it. There is also no ability to alter the number of pulses.
U.S. Pat. No. 7,155,651 describes a complex on-chip controller capable of delivering various numbers of pulses on the scan and system clocks. The number of pulses is programmable. The timing of the pulses is determined by two “reference clocks,” the “functional clock” used during normal operation and a separate shift clock. It does not appear to be possible, let alone convenient, to alter the frequency of the clocks and thus the delay from launch to capture.
U.S. Pat. No. 7,202,656 describes a scheme for “launch from capture” testing. An on-chip PLL provides a high-frequency output, and an on-chip pulse counter passes exactly two pulses from the PLL output to the system clock. The delay between the two pulses can only be controlled by adjusting the PLL frequency, which is not always convenient.
U.S. Pat. No. 7,375,570 describes a scheme for “launch from capture” testing where the launch and capture pulses are both delivered over a single system clock. The length of each pulse is controlled by an on-chip delay line. The launch and capture pulses are triggered by two separate signals from the tester with rapid and precise relative timing. Not all testers are capable of providing such signals.
Persons of ordinary skill in the art will observe that none of these prior art methods provide a convenient way to control the launch-capture interval. They either require a sophisticated tester, or a clock whose period equals the desired interval or is an exact multiple of the desired interval. In particular, there is no way to achieve fast launch-capture intervals that are less than the minimum clock period.
Several other methods for delay testing have been developed specifically for FPGAs which take advantage of their programmability.
U.S. Pat. No. 6,356,514 describes a method for measuring delays through logic in an FPGA. The chip is programmed to implement one or more free-running ring oscillators which include the desired delay path. The output of the oscillator is connected to on-chip counters to measure its frequency and duty cycle. It is not clear from this reference if the counters are intended to be built with programmable logic or hard circuitry.
This scheme has several disadvantages. First, clock-to-output delays through flip-flops may only be incorporated into the ring by adding delay elements to reset the flip-flop after some suitable delay, which must be safely below the period of the oscillator. In addition, the scheme does not appear to support measurement of setup times at flip-flop inputs. Further, some of the programmable logic and routing is consumed to either implement the counters or convey the oscillator outputs to a central hard-logic counter. This increases the number of test designs that are required to be sure all circuitry is included in at least one ring oscillator. If a central hard counter is used, it may become a bottleneck preventing testing of multiple oscillators simultaneously, increasing test time.
Another category of delay testing methods for FPGAs works by detecting differences in delay on pairs of paths with matching nominal delay (i.e. two equivalent paths that should have identical delays). If the actual delays of the matched paths differ significantly, it indicates a defect. Two such methods have been described in the prior art.
E. Chmelar, “FPGA Interconnect Delay-Fault Testing,” Proc. Int'l Test Conf. (ITC 03), 2003, pp. 1239-1247, describes a delay fault test technique using paths of matched nominal delay in an FPGA with a special delay mismatch detection circuit. However the delay mismatch tolerance is determined by the actual delay of a certain routing path, which is quite inflexible. Altering the tolerance requires reprogramming the FPGA to insert or remove routing resources in the path. Reprogramming the FPGA unnecessarily increases total test time.
M. Abramovici and C. Stroud, “BIST-based delay-fault testing in FPGAs,” Journal of Electronic Testing: Theory & Applications, Vol. 19, No. 5, pp. 549-558, 2003, suggest using paths of matched nominal delay in FPGAs and detecting mismatches using a counter. Their approach has several disadvantages. The use of counters has the same drawbacks cited above in connection with the ring oscillator scheme. The precision of the delay discrimination is limited by the maximum frequency of the counters. Finally, if a central counter is used, it is difficult to convey the high-speed pulses from the ends of the paths under test to the central counter.
For volume production it may sometimes be desirable to test FPGAs for use with a specific customer design. In this case, defects in circuitry not used by the particular design can be ignored. Even in this case however the testing is still generally performed by programming multiple test designs into the chip.